\section{Experimental Platforms}
\label{sec:platform}

\subsection{Hardware Platforms}
\subsubsection{GPU Platform: }

Quadro 600 \cite{Nvidia:Quadro-600}. It is equipped with 96 CUDA cores, and 1GBDDR3 as the video card memory. The memory interface is 128bit width, with the memory bandwidth 25.6
GB/s. The maximum power consumption is 40W.


\subsubsection{Generic CPU Platform: }
Intel Xeon E3 1245 processor. This is a quad-core processor with Hyper-Thread
enabled, which provides 8 logical hardware threads in total. The clock speed is
3.3GHz. In Intel Turbo mode, it can reach up to 3.7GHz. Each core is equipped
with 32KB Instruction and  32KB Data L1 cache, 256KB L2 Cache. All four cores
share 8M L3 Cache. It also support the latest SSE4.1/4.2, AVX SIMD instructionsets. For more detail spec, please refer to \cite{Intel:E3-1245}.

\subsubsection{FPGA Platform: }
Altera Cyclone II (2C35) FPGA. It has 35,000 Logic Elements (LEs), 64 Mb of block ram, 
2 MB sychronous SRAM, 16 MB DDR SDRAM, 16 MB flash memory, and 475 user I/Os. For more details, please refer to~\cite{Altera:DE2}.

\subsection{Software Platform}

\subsubsection{CUDA Toolkit 4.1: }
We used the latest Nvidia CUDA Toolkit 4.1 \cite{Nvidia:CUDASDK} for testing CUDA parallel
programming model and OpenCL on Nvidia GPU. 

\subsubsection{Intel OpenCL SDK 1.5: }
We used Intel OpenCL SDK 1.5 \cite{Intel:OpenCLSDK} for measuring OpenCL on
Intel Generic CPU. This version of Intel OpenCL SDK is fully conformant with the
OpenCL 1.1 specification for the CPU. It also has auto vectorization of
OpenCL code capability to utilize Intel architecture's SSE capability.

\subsubsection{Bluespec and Verilog: }
At the start of the first phase of our project we had to take a decision \textit{``whether we
should use Verilog or Bluespec to write benchmarks for FPGAs?''}. We decided to use Bluespec
because it is a strongly-typed hardware synthesis language and raises the abstraction level
for FPGA programming making it easier for the programmer. It has recently gained popularity and has been
used at Sandburst, Bluespec Inc., MIT, and CMU to describe a variety of complex
hardware designs. It is also claimed that Bluespec design approach is able to
generate RTL that is comparable to handwritten Verilog. 

However, We implemeted a pipelined parallel version of matrix multiplication similar 
to the CUDA kernel and realised that though bluespec is significantly easier to use 
than verilog, developing a finely tuned kernel takes significant amount of time. Thus, we have changed 
our strategy and would be using benchmark suites designed for embedded systems, 
most of which are written in Verilog. We shall be using Quartus II Web Edition~\cite{QuartusII} for 
synthesizing verilog to FPGA.
 
